1. Field of the Invention
Generally, the present invention relates to trench isolation structures as usually employed in sophisticated semiconductor devices to electrically insulate neighboring circuit elements from each other, and, more particularly, to techniques allowing the adjustment of characteristics of trench isolation structures, such as corner rounding and residual stress created therein.
2. Description of the Related Art
The ongoing trend in continuously improving the performance of microstructures, such as integrated circuits, not only requires a steady decrease in the feature sizes of the circuit elements but also requires a structure that reliably electrically insulates adjacent circuit elements from each other, wherein the available chip area for manufacturing isolation structures decreases as the feature sizes of the circuit elements are shrunk and the number thereof is increased. For integrated circuits having circuit elements with a feature size of approximately 1 μm and less, the well-established isolation structures such as the LOCOS (local oxidation of silicon) structure are preferably replaced by less space-consuming and more reliable isolation structures requiring the formation of a vertical trench enclosing a circuit element under consideration. In addition to the reduction of chip area occupied by the trench isolation structure compared to the LOCOS structure, the former structure provides a substantially planar surface for subsequent photolithography processes, thereby significantly improving the resolution of the photolithography process compared to the strongly varying topography of the LOCOS structure. Although the introduction of trench isolation structures into the manufacturing process of integrated circuits significantly enhances device reliability in combination with an increased package density, certain issues arise in manufacturing trench isolation structures, especially when the dimensions of the isolation structure and the associated circuit elements approach the deep sub-micron regime. For dimensions in this order of magnitude, relatively high electrical fields may be created on sharp corners of the trench isolation structures and may therefore affect the operation of the circuit elements, such as field effect transistors and capacitors and the like, finally resulting in an increased leakage current between adjacent circuit elements. The formation of a trench isolation structure generally requires the employment of photolithography and anisotropic etch techniques where, in particular, upper corners of the trenches exhibit, due to the anisotropic etch process, relatively sharp corners that may not be sufficiently rounded by controlling process parameters of the etch process. Therefore, it has become standard practice to form a thermally grown oxide on inner surfaces of the trench so as to provide for an increased radius of curvature, especially of the upper corners of the isolation trenches, wherein, however, an increased thickness of the thermally grown oxide entails additional compressive stress, which in turn may adversely affect device characteristics of the adjacent circuit element.
With reference to FIGS. 1a-1e, the fabrication of a conventional isolation structure is described in more detail. In FIG. 1a, a semiconductor structure 100 comprises a substrate 101, for example a semiconductor substrate, such as a silicon wafer, or a dielectric substrate bearing a semiconductor layer, such as an SOI (silicon on insulator) substrate. An oxide layer 102 is formed over the substrate 101, for example in the form of a silicon dioxide, followed by a further dielectric layer 103, the material composition of which may be preferably selected so as to serve as a stop layer during a CMP process required in a further advanced manufacturing stage. For example, the layer 103 may be provided as a silicon nitride layer. A resist mask layer 104 is formed over the silicon nitride layer 103 having, formed therein an opening 105, the dimensions of which substantially represent the dimensions of a trench to be formed in the substrate 101. It should be noted that, depending on the type of photolithography technique employed, the resist mask 104 may comprise an anti-reflective coating to enhance the resolution of the photolithography step.
A typical process flow for forming the semiconductor structure 100 may include the following processes. The oxide layer 102 may be formed by a conventional oxidation process or may be deposited by chemical vapor deposition (CVD) techniques from appropriate precursor gases. Next, the silicon nitride layer 103 is deposited, followed by applying a resist layer that is subsequently patterned by a photolithography process to form the opening 105. The lateral dimensions of the opening 105 may depend on the specific design of the circuit to be formed, and may require advanced photolithography techniques when, for instance, feature sizes in the range of approximately 0.2 μm and less are to be manufactured.
FIG. 1b schematically shows the semiconductor structure 100 with a trench 106 formed in the silicon nitride layer 103, the oxide layer 102 and partially in the substrate 101. The trench 106 has bottom corners or edges 107 which exhibit a rounding or a radius of curvature that depends on the specifics of the anisotropic etch process. On an upper portion of the trench, however, the interface between the oxide layer 102, the substrate 101 and the trench 106, as indicated by 108, will form a relatively sharp corner or edge which may not be easily rounded during the etch process due to the characteristics of the anisotropic etch process. Since sharp corners, e.g., the areas 108, may entail, upon application of a voltage, relatively strong electrical fields in areas adjacent to the trench 106, respective counter measures are usually taken to round the corners 107, and especially the areas 108, so as to minimize any inadvertent impact on a circuit element manufactured near the isolation trench 106, such as a field effect transistor.
Therefore, generally a thermal oxide liner is grown on inner surfaces of the trench 106 in order to provide a larger radius of curvature at the areas 108 at the interface between the dielectric silicon dioxide 102 and the material of the substrate 101. It turns out, however, that growing a thermal oxide within the trench 106 and subsequently depositing a bulk oxide for filling the trench 106 with a dielectric material may result in a reduced quality of the deposited oxide having a higher etch rate adjacent to the thermal liner oxide, thereby possibly leading to the creation of notches during the removal of the silicon nitride layer 103. Consequently, a so-called “late liner” process is frequently employed, in which the bulk oxide is deposited prior to forming the thermal oxide within the trench 106.
FIG. 1c schematically shows the semiconductor structure 100 with a silicon dioxide layer 109 formed over the trench 106 to an extent that the trench 106 is reliably filled at least up to the silicon nitride layer 103. Appropriate deposition techniques, such as chemical vapor deposition with precursor gases TEOS, oxygen and ozone at a temperature range of approximately 350-650° C., may be employed to substantially fill the trench 106 without the creation of any voids therein.
FIG. 1d schematically shows the semiconductor structure 100 with a thermal oxide layer 110 formed on oxidizable inner surfaces of the trench 106, wherein, particularly, the rounding at the areas 108 is significantly increased.
The thermal oxide layer 110 may be formed by exposing the substrate 101 to an oxidizing ambient 112 at an elevated temperature, wherein the dielectric oxide material of the layer 109 is simultaneously densified. By appropriately adjusting the process parameters of the oxidation process, a thickness of the thermal oxide layer 110 may be adjusted in accordance with design requirements. Although an increased thickness of the thermal oxide layer 110 is advantageous in view of increasing the rounding, i.e., the radius of curvature, of the areas 108, it turns out, however, that a mechanical stress 111 is created within the trench 106, since the volume of the thermal oxide created in the layer 110 exceeds the volume of the consumed silicon of the substrate 101. The mechanical stress 111 induced by the growth of the thermal oxide layer 110 may, however, negatively affect the device characteristics of adjacent circuit elements, for example by producing lattice damage in the crystalline structure, and may even increase when high temperature anneal cycles are carried out during the further manufacturing steps. Therefore, a trade-off has to be made regarding the required degree of rounding of the areas 108 and the amount of acceptable mechanical stress 111 created by the thermal oxide layer 110. Since a plurality of different circuit elements having a different sensitivity to undesired electric fields and compressive stress are usually manufactured in an integrated circuit, the isolation trenches 106 represent a targeted compromise for the most sensitive type of circuit elements.
FIG. 1e schematically shows the semiconductor structure 100 after the removal of excess material of the oxide layer 109 by chemical mechanical polishing (CMP). The thickness of the silicon nitride layer 103, acting as a CMP stop layer, is also reduced during the CMP process, wherein the initial thickness of the silicon nitride layer 103 is selected so as to substantially ensure the integrity of the substrate 101 across the entire substrate surface. Subsequently, the residual silicon nitride layer 103 and thereafter the oxide layer 102 may be removed by appropriate wet chemical etch processes (not shown).
In view of the problems resulting from the trade-off in forming the thermal oxide layer 110 that has to be tailored to specific circuit elements, it would, therefore, be highly desirable to provide a technique for the formation of trench isolation structures which allows a higher degree of flexibility in adapting the trench isolation to a specific circuit element.